CMOS Process Variations: A Critical Operation Point Hypothesis

April 2, 2008 lecture by Janak H. Patel for the Stanford University Computer Systems Colloquium (EE380).

Prevailing understanding of a chip's behavior under large process variations with statistical delay assumptions leads one to conclude that a small number of errors are likely as we progress further down on Moore's Law. This understanding is challenged by a new hypothesis which states that in every large CMOS chip, there exist critical operations points (frequency, voltage, temperature) such that it divides the 3-D space in to two distinct spaces: Error-free operation and Massive errors.

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